A system has a level 1 cache and a level 2 cache. The hit rate of the level 1 cache is 95%, and the subsequent hit rate of the level 2 cache is 80%. An access to level 1 cache requires one cycle, and access to level 2 cache requires 3 cycles, and an access to main memory requires 80 cycles. What is the average access time in clock cycles?

Step-by-step explanation:

H1 = Hit rate of level 1 cache = 0.95

T1 = Access time for level 1 cache = 1

H2 = Hit rate of level 2 cache = 0.8

T2 = Access time for level 2 cache = 3

Hm = Hit rate of Main Memory = 1

Tm = Access time for Main Memory = 80

Average access time = [H1*T1]+[(1-H1)*H2*T2]+[(1-H1)(1-H2)*Hm*Tm]

= [0.95*1]+[1-0.95]*0.8*3]+[(1-0.95)(1-0.8)*1*80]

= [0.95+0.05*0.8*3]+[0.05*0.2*1.80]

= 2.4+0.018 = 2.418

Average access time = 2.418

anser is a

step-by-step explanation:

negitive slope