The Hamming encode/decoder in the lecture detected and corrected one error bit. By adding a thirteen bit which is the exclusive-OR of the other twelve bits, double bit errors can be detected (but not corrected). Add this feature to the example and modify the noisy channel so that sometimes two bits are in error. Change the $display statement to indicate the double error. See the additional supplemental information about the 13-bit Hamming code. Please show all the Verilog codes for your design. The basic Hamming code can detect and correct an error in only a single bit. Some multiple-bit errors are detected, but they may be corrected erroneously, as if they were single-bit errors. By adding another parity bit to the coded word, the Hamming code can be used to correct a single error and detect double errors. If we include this additional parity bit, the previous 12-bit coded word becomes 001110010100P 13, where P13 is evaluated from the exclusive-OR of the other 12 bits. This produces the 13-bit word 0011100101001 (even parity). When this word is read from memory, the check bits and also the parity bit P are evaluated over the entire 13 bits. If P = 0, the parity is correct (even parity), but if P = 1, the par- ity over the 13 bits is incorrect (odd parity). The following four cases can occur: If C = 0 and P = 0 If C+0 and P = 1 If C+0 and P = 0 No error occurred. A single error occurred that can be corrected. A double error occurred that is detected but cannot be corrected. An error occurred in the P13 bit. If C = 0 and P= 1 Note that this scheme will detect more than two erroneous bits in many cases, but is not guaranteed to detect all such errors. A modified Hamming code to generate and check parity bits for a single- error-correction, double-error-detection scheme is most often used in real systems. The modified code uses a different parity check bit scheme that balances the num- ber of inputs to the logic for each check bit and thus the number of inputs to each circuit that does the checking. The balancing minimizes the delay through the error correction and detection circuits. These circuits can be used in a RAM subsystem to add check bits during write operations and to correct single errors and detect dou- ble errors during read operations.