ROM Design 1. Requirement
Design ROM that has 16 locations each 32 bits wide. The 16 locations have the values like 0xDEADBEEF, 0xCAFEBABE, 0xDEADFEED and so on of your choice. There will be a chipselect (CS) input that activates the chip. The address input to the chip is a vector. The output would also be a vector that should send out the data already initialized at the active clock edge, depending on the address input to the chip.
Clk
CS ROM 16x32 Data Out
Addressbits
The interface can be as below:
entity ROM 32Bits_Design is
port
Clk:instd logic
cs:instd logic:
Address:instd logic vector (3downtoo)
Data Out :outstd logic_vector (31 downto0)
2. Pre-lab
Study and analyze the working of a ROM
Study how to do the type conversion in VHDL:
std logic vector
signed/un-signed signed/un-signed Intege
std_logic_vector?integer
3. Lab
Write the VHDL code for this ROM design(recommend using conversion functions located in numeric std library for index conversion for array).
Simulate using Xilinx Vivado simulator.
VHDL test bench with enough test cases.