Construct the D-flip-flop with negative edge triggering using any number of inverters and transmission gates (no asynchronous clear is needed). The design goal is to obtain a small propagation delay from D to Q after the negative clock edge. The circuit inputs are D, CLOCK; there is only one output Q. Hint: for the Master D-latch output use the complement of Q. Show the schematic using inverters and transmission gates as building blocks.

For each of the following process: a) sketch the p-v diagram, b)sketch t-s diagram, c) sketch t-v diagram, d) sketch the boundary work on one of the diagrams (a, b or c) and e) sketch the reversible heat transfer on one of the diagrams (a, b or c): 1- isobaric process from compressed liquid to superheated vapor 2- isothermal process from compressed liquid to superheated vapor 3- isentropic process from compressed liquid to superheated vapor