Create a project called Exp_9, then create the Verilog file describing the circuit above. Create a test bench and then simulate your circuit. Check the simulation for correctness of your design then synthesize, fit, and program the circuit into FPGA. Test circuitry for correct functionality. The signals of the circuit should be connected to the following locations on the FPGA board: Inputs Start/Stop – button (Debouced button BTN1 on external board); Clock – button (Debouced button BTN2 on external board); Input for parallel load into SR1 from switches (SW3 – SW0);