Engineering, 11.04.2020 02:51, fatback7063

The specifications of the decoder are re-stated as follows: - 32-word register file - 64-bit words - Each register bit presents a load of three unit-sized transistors on the word line - True and complementary versions of the address bits A[4:0] are available - Each address input can drive 10 unit-sized transistors Determine

1) the fastest decoder design, and estimate
2) the delay of the decoder and
3) transistor widths to achieve this delay.

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The specifications of the decoder are re-stated as follows: - 32-word register file - 64-bit words -...