Engineering, 03.04.2020 16:17, jojokeys

Write two different behavioral Verilog descriptions of the JK FF with an active-low asynchronous reset (i. e. a global reset input to the FF), as follows:
(a) Derive the characteristic equation when Q=0 or Q=1. In your code, use an if-else statement based on the value of the present state in either of these cases. (b) In your code, use an if-else statement to specify how the J and K inputs affect the outputs of the FF at each clock tick (Do not rely on the characteristic equations).

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Write two different behavioral Verilog descriptions of the JK FF with an active-low asynchronous res...