1. Purpose:
Design a stopwatch using counters.

2. Prelab:
Design and simulate the circuit in Section 5.

3. Discussion:
Discussion 3.1
Generation of clock signal in simulation A system clock is frequently needed to simulate a sequential system. For the FPGA device on the DEI board, a 200-ns clock allows enough time for the circuit to settle down and provides a good visual observation. In Quartus II, it can be derived as follows:
Invoke the waveform editor and insert the clock signal.
• Select Edit and then Grid Size. Enter 100 ns. Select Edit and then Set End
• Time to specify the maximal simulation time. Determine the number of clock cycles needed and then enter the value. For example, enter 20 us if 100 cycles are desired (i. e., 100*200ns-20us)
• Highlight the clock signal in waveform editor and then click the clock-like icon and a sub-window appears. Enter 200 ns for the clock period and 50% for the duty cycle. The clock signal will be generated for the entire simulation period.
The input signal patterns can be entered afterward. The change of input value should be occurred at the falling edge of the clock signal to avoid setup time violation.

4. Project description:
We wish to design a two-digit stopwatch by using 74163s. The watch has the following input:
• clk: clock signal
• clear: clear the stopwatch to 00
• go: the stopwatch counts when go is 1 and pause (ie, keep the current value) when go is 0.

The output of the stopwatch is two seven-segment LED displays indicating the current count. The displays should be in BCD (binary coded decimal) format and count from 00 to 99. The stopwatch wraps around when reaching 99. In other words, the counting sequence is:
00, 01, 02, ..., 09, 10, 11, 12,..., 19, 20, 21, 22, ..., 98, 99, 00, 01, 02,

5. Procedure 5.1:
Decade counter (mod-10 counter) A decade counter counts from 0 to 9 and warps around. Its inputs are:
• clk 10: clock signal
• clear 10: clear the counter to 00
• en 10: enable the counting when en 10 is 1 and pause otherwise.
Its outputs are:
• 93, 92. 91.90: 4-bit counting value (93 is MSB)
• p10: an output pulse asserted when the counting value is 1001 and en 10 is 1.

Required:
(a) Design the decade counter using one 74163 and a minimal number of basic gates.
(b) Create a project in Altera Quartus II software and enter the schematic.
(c) Create a testing waveform with a clock period of 200ns.