Engineering
Engineering, 11.12.2019 18:31, alexsk6357

Design a 4-bit synchronous up/down counter using combinational logic and dffs resettable to zero, with inputs: clk, reset, and inc/dec, and output: count(3: 0), such that upon reset count = "", count++ = count- – β€ž1β€Ÿ when inc/dec = β€ž0β€Ÿ, and count = count- + β€ž1β€Ÿ when inc/dec = β€ž1β€Ÿ. when inc/dec = β€ž1β€Ÿ and count- = "", count+ = ""; and when inc/dec = β€ž0β€Ÿ and count- = "", count+ = "".

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Design a 4-bit synchronous up/down counter using combinational logic and dffs resettable to zero, wi...

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