Design the nmos gain stage with a pmos current mirror load as shown in figure 1 with the following specifications

external capacitive load: 100 ff

slew rate: > 1 v/ns

dc differential gain: > 40 db

– 3 db bandwidth: > 10 mhz

amplitude of ac output voltage: > 0.8 v.

cmrr at low frequencies: > 80 db

for simplicity select vgs_n = 0.8 v for the nmos devices in the differential pair. vgs_p for the pmos in the current mirror can be selected in a broad range as long as the nmos devices in the differential pair operate in the saturation region.

b) for your design estimate the following parameters:

voltage range for common-mode input signal: vicm_max, vicm_min