Project stem 7.6 lesson practice For Questions 1-4, consider the following code:

def mystery(w):
if (w. upper() == w. lower()):
return "TRUE"
else:
return "FALSE"

:you areto design the controller for alight that functions both as an ordinary light and also as a motion activated light and alarm. a. if the manual switch s is on, then the light l is on. b. besides the manual switch, there is a motion detector, m1, which activatesthis light. c.if motion is detected but the light is on anyway because s is on, only then a secondoutput a, an alarm, is turned on. d. the disable switch, d, disables the motion activated light and alarmbut leaves manual control operation of the light using switch s.(i)read the problem statement and clearly identify the inputs and outputs for the circuit you are designing. (ii)create the truth table for this system; include the light, alarm, switch, disable, and the motion sensor.(iii)draw a schematic of this system.

When making changes to optimize part of a processor, it is often the case that speeding up one type of instruction comes at the cost of slowing down something else. for example, if we put in a complicated fast floating-point unit, that takes space, and something might have to be moved farther away from the middle to accommodate it, adding an extra cycle in delay to reach that unit. the basic amdahl's law equation does not take into account this trade-off. a. if the new fast floating-point unit speeds up floating-point operations by, on average, 2ă—, and floating-point operations take 20% of the original program's execution time, what is the overall speedup (ignoring the penalty to any other instructions)? b. now assume that speeding up the floating-point unit slowed down data cache accesses, resulting in a 1.5ă— slowdown (or 2/3 speedup). data cache accesses consume 10% of the execution time. what is the overall speedup now? c. after implementing the new floating-point operations, what percentage of execution time is spent on floating-point operations? what percentage is spent on data cache accesses?

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