The base CPI of a system, excluding both memory and cache accesses, is C. Loads and stores collectively constitute LS% of all instructions Accessing the L1 data cache takes LD cycles (accounted for in base CPI). Accessing the L1 instruction cache takes LI cycles (accounted for in base CPI). Misses to main memory take an average of D cycles. The L1 D-cache miss rate/access is MD. The L1 I-cache miss rate/access is MI. Our research team tries to provide the solution to increase different characteristics of the system. First, suppose we want to improve the AMAT for our system by placing an L2 Cache with 4*LD access time. How high can be the miss rate so we can still improve the AMAT?