Suppose that we have 10,000 lines in our program. Suppose that our computer has four pipelinestages. Suppose that the program has the followingcharacteristics: 2% of instructions are branch instructions. 20% ofbranch instructions require theinsertion of 1 NOP each (for the other 80% of branchinstructions, instructionreordering is used.)
5% of instructions are memory reads, and the cachehit rate is 80%. All memoryaccesses that miss the cache can be found in mainmemory. Reading from mainmemory takes 10 clock cycles. We use a write backand write-allocate policy. Writing to main memory takes 10 clock cycles. Reading fromand writing to main memorycannot take place simultaneously. Assume that whena cache entry needs to bereplaced, 20% of the time the dirty bit is 1
5% of instructions are memory writes, and the cachehit rate is 90%. We use a writeback and write-allocate policy. Writing to main memorytakes 10 clock cycles. Reading from and writing to main memory cannot takeplace simultaneously. Assumethat when a cache entry needs to be replaced, 20%of the time the dirty bit is 1.

The clock period is 10ns.

Required:
a. How many cycles would it take to run the entire program if there were no stalls?
b. How many additional cycles would be caused by branch instructions?
c How many additional cycles would be caused by memory read instructions?
d. How many additional cycles would be caused by memory write instructions?