Consider a pipelined processor with just one level of cache. Assume that in the absence of memory delays, the baseline CPI of this processor is 2. Now assume that the percentage of memory instructions in a typical program executed on this CPU is 50% and the memory access latency is 150 cycles. Assuming that the I-cache delays are already accounted for in the baseline CPI, consider the following two alternatives for the D-cache design: Alternative 1: A small D-cache with a hit rate of 94% and a hit access time of 1 cycle (assume that no additional cycles on top of the baseline CPI are added to the execution on a cache hit in this case).
Alter tive 2: A larger D-cache with a hit rate of 98% and the hit access time of 2 cycles (assume that every memory instruction that hits into the cache adds one additional cycle on top of the baseline CPI).
a) [5%] Estimate the CPI metric for both of these designs and determine which of these two designs provides better performance. Explain your answers
b) [5%] Repeat part (a), but now assume that the memory access latency is reduced to 50 cycles.
c) [5%] Repeat part (b), but now assume that the L2 cache is also added to the system with the hit rate of 75% and access latency of 10 cycles.