A non-pipelined processor has a clock rate of 1 GHz and an average instruction takes 9 cycles to execute. The manufacturer has decided to design a pipelined version of this processor. For this purpose, the instruction cycle has been divided into five stages with the following latencies: Stage 1 – 2.0 ns, Stage 2 - 1.5 ns, Stage 3 – 1.0 ns, Stage 4 – 2.6 ns, Stage 5 – 1.9 ns. Each stage will require an extra 0.4 ns for the buffers between the pipeline stages, including the last stage. a) What clock cycle time will be required for the pipelined processor? What will be the corresponding clock rate?
b) What will be the execution time for a single instruction in the pipelined processor? What is the percentage increase compared to the non-pipelined processor?
c) What is the maximum throughput of the pipelined processor expressed as MIPS? What is the speedup over the non-pipelined processor?
For the pipelined processor of Problem above, it has been suggested that perhaps a better approach would be to have only four stages with Stages 2 and 3 above being merged into a single stage. Assume that the extra time for the inter-stage buffers is still 0.4 ns for each stage. Repeat parts (a), (b), and (c) of Problem 4 for this situation.
d) Compare this processor with the five-stage processor of Problem 4. Which design should be preferred, and why?