Computers and Technology

The CPI for an ideal 5-stage pipeline that is always full is 1. Assume a code with no data hazards, and no delay slots are used, but with 25% of branch instruction. Assume that branch outcomes are determined in the ID stage and a misprediction causes a cycle delay. Also assume the following branch predictor accuracies. Always Taken Always Not taken 2-Bit
45% 55% 85%

a. Stall cycles due to mispredicted branches increase the CPI. What is the extra CPI due to mispredicted branches with the always-taken predictor?
b. What is the extra CPl due to mispredicted branches with the always-not-taken predictor?
c. What is the extra CPl due to mispredicted branches with the 2-bit predictor?

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The CPI for an ideal 5-stage pipeline that is always full is 1. Assume a code with no data hazards,...

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