Computers and Technology

Computers and Technology, 14.10.2019 03:30, jc624826

In reference to access time to a two-level memory, a occurs if an accessed word is not found in the faster memory.

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Computers and Technology, 13.07.2019 01:20, estheradame547

Consider a demand-paging system with a paging disk that has an average access and transfer time of 50 ms. addresses are translated through a page table in main memory, with an access time of 2 us per memory access. thus, each memory reference through the page table takes two accesses. to improve this time, we have added an associative memory (tlb) that reduces access time to one memory reference, if the page-table entry is in the associative memory (tlb). ssume that 90% of the accesses are in the associative memory (tlb), and that, of the remaining, 20%) or 2% of the total) cause page faults, what is the effective memory access time?

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Computers and Technology, 21.08.2019 18:20, surpremeblizzle

Consider a demand-paging system with a a paging disk that has an average access and transfer time of 50 ms. addresses are translated through a page table in main memory, with an access time of 5 us per memory access. thus, each memory reference through the page table takes two accesses (i.e. 10 us). to improve this time, we have added an associative memory (tlb) that reduces access time to 6 us, if the page-table entry is in the associative memory. assume that 60% of the accesses are in the associative memory, and that, of the remaining, 10% (or 4% of the total) cause page faults. what is the effective memory access time?

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Computers and Technology, 27.11.2019 23:31, 7letters22

A32-bit dlx computer transfers a 512-byte sector (128 words) from the hard disk to the main memory by using dma. the disk reads the sector from the platter into a special memory called the disk cache which is part of the disk controller. thereafter the data is transmitted from the disk cache to the main memory via the bus by using dma. compute this dma transfer time from disk cache to main memory. the following are the parameters we know: ï¿½ the bus is 4 words wide and the time to propagate a signal on the bus is 4 processor cycles. (this is often called the bus cycle time.) ï¿½ the disk cache is 1 word wide and has an access time of 1 processor cycle. ï¿½ the main memory is 16 words wide and has an access time of 80 processor cycles. assume that main memory accessed cannot be pipelined (i.e., we must wait for the previous access to finish before the next access can be issued. the process of transfer is as follows. first, four words are read from the disk cache into hardware registers. when done, they are sent together on the bus in one transfer. when four successive bus transfers are received at the memory, they are written together to the memory. different stages in this process are overlapped (pipelined) to the extent possible -- carefully think through what can be overlapped.

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In reference to access time to a two-level memory, a occurs if an accessed word is not found in the...

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