Assume that the following code segment is run on a MIPS processor with hazard detection and forwarding, in order, 5 stages pipeline (F (instruction fetch), D (instruction decode), E (execute). M(memory access, W (write-back)), static not taken branch prediction (branches are always predicted as not taken), etc.. Below is the code segment that is running on the processor. # code segment bge $R1, SRO, L2 sw $R2, 100(SR1) # $R2 -> MISR1 +100] sh1 $R2, $R2, 1 beq $RO, SRO, L3 L2: lw SR2, 100(SR1) #M[$R1+100] -> SR2 addi $R2, SR2, 100 addi $R3, $R3, 1
beq SRO, SRO, STR L3:
END L1:
a) How many cycles does this program take? Assume all data and instructions are already in the cache, and that all register values are initially 0. The branches are always going to be evaluated as "not taken" and they require two stall clock cycles each.
b) An optimizing compiler is used to re - write re-order the code for faster execution. Given that the branches are always going to be "not taken", how would the new code look like? How many cycles would the code take?