Which of these statements is true of dynamic design diagrams

Acomputer has a two-level cache. suppose that 60% of the memory references hit on the first level cache, 35% hit on the second level, and 5% miss. the access times are 5 nsec, 15 nsec, and 60 nsec, respectively, where the times for the level 2 cache and memory start counting at the moment it is known that they are needed (e. g., a level 2 cache access does not even start until the level 1 cache miss occurs). what is the average access time?

How many points do i need before i can send a chat

Perform an online search about the booting process of a computer and list all the steps