On computer X, a nonpipelined instruction execution would require 12 ns, and thus 12 ns exists between instructions. A pipelined implementation uses 6 equal-length stages of 2 ns each, resulting in ns between instructions.

2ns

Explanation:

Given that after 2 ns, a first instruction Instr1 would be accomplished with stage 1. This implies that Instr2 could commence in stage 1. It should be noted that 1ns is too short: that is, Instr1 would only be halfway through stage 1, thereby Instr2 began to use stage 1, leading to a problem.

Also, the general equation is 12 ns / 6 stages which equals 2ns between instruction.

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