A full adder can be built from 2 half adders and an OR gate. The following verilog code show a hierarchical description of such a full-adder built from 2 half adders and an OR gate. Fill in the blanks. module half_adder(x, y,s, c);

input x, y;
output s, c;
xor(s, x,y);
and(c, x,y);
endmodule
//Full adder verilog module
//a, b, cin(carry-in) are the inputs to the full adder
//s(sum) and cout(carry out) are the outputs of the full adder
//The sum of half adder1 is s1 and carry is c1
//The sum of half adder2 is s and carry is c2
module full_adder(a, b,cin, s,cout);
input a, b,cin;
output s, cout;
wire s1,c1,c2;
half_adder ha1(a, b,(),c1);
half_adder ha2(cin, s1,s,());
or((),c1,c2);
endmodule

8. create an abstract student class for parker university. the class contains fields for student id number, last name, and annual tuition. include a constructor that requires parameters for the id number and name. include get and set methods for each field; the settuition() method is abstract. create three student subclasses named undergraduatestudent, graduatestudent, and studentatlarge, each with a unique settuition() method. tuition for an undergraduatestudent is $4,000 per semester, tuition for a graduatestudent is $6,000 per semester, and tuition for a studentatlarge is $2,000 per semester. write an application that creates an array of at least six objects to demonstrate how the methods work for objects for each student type. save the files as student. java, undergraduatestudent. java, graduatestudent. java, studentatlarge. java, and studentdemo. java.