10. Let the worst case propagation delay for a NOT gate be 10 ns (nanoseconds, 10-9 sec), for 2-input logic gates be 20 ns, for 3-input logic gates be 24 ns, and for 4-input logic gates be 28ns. From lecture slide 29 we have the Boolean SOP expression m = x’yz + x’yz’ + x’y’ + xyz and its simplified form m = x’ + xyz Assume that only the positive logic inputs x, y, and z are available, meaning that x’, for example, must be computed using a NOT gate if x’ is needed. How much less than that for the original expression is the worst case propagation delay for the simplified form?