How do you write a VHDL code for this

The SecondGenerator block generates the second count i. e; it increments an internal variable once every second from 0 to 59 and then rolls back to 0. That (std_logic_vector) variable can be assigned to a (std_logic_vector) signal second[5..0] which comes out of the block. Note that this is a 6-bit std_logic_vector value because counts up to 59 can be accommodated in 6 binary digits (26 = 64). As most clocks do not display second counts so this value is not utilized any further here. This block also generates a pulse every time the second counter rolls over i. e. every 1 minute. This comes out as the std_logic signal minute_out .