Design a 4-bit register with both shift and parallel load features. The inputs of the register include a 2-bit control code X Y, a 4-bit input value I3 I2 I1 I0, and a clock signal. The outputs of the register are the 4 bits Q0 Q1 Q2 Q3 corresponding to the value stored in the register. You are allowed to use any number of D flip-flops, muxes of any size, decoders and encoders of any sizes, AND gates, OR gates, and NOR gates. (Notes

The idea that, for each pair of devices v and w, there’s a strict dichotomy between being “in range” or “out of range” is a simplified abstraction. more accurately, there’s a power decay function f (·) that specifies, for a pair of devices at distance δ, the signal strength f(δ) that they’ll be able to achieve on their wireless connection. (we’ll assume that f (δ) decreases with increasing δ.) we might want to build this into our notion of back-up sets as follows: among the k devices in the back-up set of v, there should be at least one that can be reached with very high signal strength, at least one other that can be reached with moderately high signal strength, and so forth. more concretely, we have values p1 ≥ p2 ≥ . . ≥ pk, so that if the back-up set for v consists of devices at distances d1≤d2≤≤dk, thenweshouldhavef(dj)≥pj foreachj. give an algorithm that determines whether it is possible to choose a back-up set for each device subject to this more detailed condition, still requiring that no device should appear in the back-up set of more than b other devices. again, the algorithm should output the back-up sets themselves, provided they can be found.\