True and False Questions. Give reasons for your answers.

(a) Allowing jumps, branches, and ALU instructions to take fewer clock cycles than the five required by the load instruction will increase pipeline performance under all circumstances.

(b) Trying to allow some instructions to take fewer cycles does not help, since the throughput is determined by the clock cycle. (It is true that the number of pipe stages per instruction affects latency, not throughput.)

(c) Allowing jumps, branches, and ALU operations to take fewer cycles only helps when no loads or stores are in the pipeline, so the benefits are small. (d) Since branches and jumps can take fewer cycles, there is some opportunity for improvement in pipelining performance. (You cannot make ALU instructions take fewer cycles because of the write-back of the result.)

(e) We could improve performance if instead of trying to make instructions take fewer cycles, we explore making the pipeline longer, so that instructions take more cycles, but the cycles are shorter.

a. FALSE

b. TRUE

c. TRUE

d. TRUE

e. TRUE

Explanation:

a) The statement “Allowing jumps, branches, and ALU instructions to take fewer clock cycles than the five required by the load instruction will increase pipeline performance under all circumstances” is false.

Explanation:

Generally, 30% of instruction in a program are in the form of branches and hence, they reduce the throughput(performance) of the pipeline.

b) The statement “Trying to allow some instructions to take fewer cycles does not help, since the throughput is determined by the clock cycle. (It is true that the number of pipe stages per instruction affects latency, not throughput.)” is true.

Explanation:

During each clock cycle, 100% utilization of pipeline is done when every stage is utilized. Pipeline does not reduce the latency as it improves the overall instruction’s throughput.

c) The statement “Allowing jumps, branches, and ALU operations to take fewer cycles only helps when no loads or stores are in the pipeline, so the benefits are small” is true.

Explanation:

Using of jumps, branches, and ALU operations can be considered acceptable only for small instruction set. If the instruction set becomes lengthy, then it is better to use the multi-cycle design of pipeline.

d) The statement “Since branches and jumps can take fewer cycles, there is some opportunity for improvement in pipelining performance. (You cannot make ALU instructions take fewer cycles because of the write-back of the result.)” is true.

Explanation:

The improvement of pipeline can be done using write-back stage. This stage transfers the result back to the register file in the middle of the data path.

e) The statement “We could improve performance if instead of trying to make instructions take fewer cycles, we explore making the pipeline longer, so that instructions take more cycles, but the cycles are shorter” is true.

Explanation:

Pipeline improves the throughput of the instruction set. Hence, pipelining can not decrease the time to complete the load of the instructions. Improvement in throughput decreases the total time to complete the instruction.

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