Assume we have a computer where the CPI is 1.0 when all memory accesses (including data and instruction accesses) hit in the cache. The cache is a unified (data + instruction) cache of size 256 KB, 4-way set associative, with a block size of 64 bytes. The data accesses (loads and stores) constitute 50% of the instructions. The unified cache has a miss penalty of 25 clock cycles and a miss rate of 2%. Assume 32-bit instruction and data addresses. Now, answer the following questions

a) What is the tag size for the cache?
b. How much faster would the computer be if all memory accesses were cache hits?

Ou listened to a song on your computer. did you use hardware or software?

After you clean an engine with hot water spray, it seems to stall; when it doesn't stall, it's idling noisily. technician a says to check for loose bolts on the flex plate near the torque converter. technician b says to wipe down the spark plug wires and the distributor cap. who is correct? a. technician a b. both technicians a and b c. technician b

Write a program in plp assembly that counts up by one starting from zero (or one) inside a loop and writes this value to the leds every time the value is increased. the memory address of the leds is 0xf0200000. the table below shows the meaning and an example usage of the instructions covered in the video, plp instructions for project 1. instruction example usage meaning load immediate li $t0, 8 register $t0 is set to the value, 8. store word sw $t2, 0($t1) the value in register $t1 is used as the memory address. the value in register $t2 is copied into this memory address. add addiu $t4, $t3, 29 register $t4 is assigned the sum of 29 and the value in register $t3. jump j your_label_name the program jumps to the line following the label, "your_label_name: ". label your label name: defines a label called "your_label_name: " that can be jumped to