Assume we have a processor with a single functional unit that handles memory operations (load/store), one functional unit that handle addition, one functional unit that handles multiply operations and one functional unit that handles divisions. Each functional unit can execute when the inputs to that functional unit are ready -- the performance is only limited data dependences, pipeline latencies and pipeline issue rates.

The following table shows the number the latency and issue cycles for each operation:

Operation Latency Issue
Add / Sub 11 11
Multiplication 22 22
Division 1515 1515
Memory load 22 22
Memory store 22 22

How many cycles would the following 64-bit Intel code sequence take? In other words, at what cycle would the last instruction complete?

Operation Cycle Completed?
movl 4(%rsp), %eax
movl 8(%rsp), %edi
addl %eax, %edi
imull %edi, %eax
movl %edi, 8(%rsp)
You can use an expression if that's useful.