For these problems, we will explore a pipeline for aregister-memory architecture. The architecture has two instructionformats; a register-register format and a register-memory format. There is a single-memory addressing mode (offset + baseregister).
There is a set of ALU operations with format
ALUop Rdest, Rsrc1, Rsrc2
or
ALUop Rdest, Rsrc1, MEM
where the ALUop is one of the following: Add, Subtract, And, Or, Load (Rsrc1 ignored), Store. Rsrc or Rdest are registers. MEMis a base register and offset pair.
Branches use a full compare of two registers and arePC-relative. Assume that this machineis pipelined so that a newinstruction is started every clock cycle. The following pipelinestructure -- similar to that used in the VAX 8700 micropipeline[Clark 1987] -- is

IF RF ALU1 MEM ALU2 WB
IF RF ALU1 MEM ALU2 WB
IF RF ALU1 MEM ALU2 WB
IF RF ALU1 MEM ALU2 WB
IF RF ALU1 MEM ALU2 WB
IF RF ALU1 MEM ALU2 WB

The first ALU stage is used for effective address claculationfor memory references and branches. The second ALU cycle is usedfor operations and branch comparison. RF is both a decode andregister-fetch cycle. Assume that when a register readand a register write of the same register occur in the sameclock the write data is forwarded.
a. Find the number of adders needed, counting any adder orincrementer; show a combination of instructions and pipe stagesthat justify this answer. You need only give one combination thatmaximizes the adder count.
b. Find the number of register read and write ports andmemory read and write ports required. Show that your answer iscorrect by showing a combination of instructions and pipeline stageindicating the instruction and the number or read ports and writeports required for that instruction.
c. Determine any data forwarding for any ALUs that will beneeded. Assume that there are separate ALUs for the ALU1 and ALU2pipe stages. Put in all forwarding among ALUs needed to avoid orreduce stalls. Show the relationship between the two instructionsinvolved in forwarding using the format of the table in Figure A.22but ignoring the last two columns. Be careful to considerforwarding across an intervening instruction, for example,
ADD R1, . . .
any instruction
ADD , R1,
d. Show all data forwarding requirements needed to avoid orreduce stalls when either the source or destination unit is not anALU. Use the same format of Figure A.22, again ignoring the lasttwo columns. Remember to format to and from memoryreferences.
e. Show all the remaining hazards that involve at least oneunit other than an ALU as the source ro destination unit. Use tablelike that in Figure A.21, but listing the length of hazard in placeof the last column.
f. Show all control hazard types by example and state thelength of the stall. Use a format like Figure A.11, labelling eachexample.