Assume a VLIW processor can support two memory references, one floating-point operation, and one integer ALU operation (including branch) per cycle. For the following code, show the VLIW code that unrolls the loop four times. Note: you should schedule the operations to fill the operation slots as much as possible. Assume there are a one-cycle stall between a load and its dependent operation, a one-cycle stall between an integer operation and its dependent branch operation, and a two-cycle stall between a FP operation and its dependent store operation. Loop: fld f2, 0(x3) fld f4, 0(x2) fadd. d f6, f2, f4 fsd f6, 0(x3) addi x3, x3,