Consider the following program and cache behaviors. data reads per 1000 instructions data writes per 1000 instructions instruction cache miss rate data cache miss rate block size (bytes) 250 100 0.30% 2% 64 5.7.1 [10] < §§5.3, 5.8> suppose a cpu with a write-through, write-allocate cache achieves a cpi of 2. what are the read and write bandwidths (measured by bytes per cycle) between ram and the cache? (assume each miss generates a request for one block.)