Write a vhdl process as a clock divide‐by‐2 function. the new clock signal should be called clkhalf'' and the input clock signal is called clk.

also include the testbench code.

signal clkhalf : std_logic : = '0';

process (clk)

begin

if (clk = '1') then clkhalf < = not (clkhalf);

end if;

end process;

You need to design a circuit that implements the functions in the following table: s0 s1 function0 0 a + 10 1 a – b1 0 a + b1 1 a – 1s0 and s1 are 1-bit control inputs to select the function of the circuit. inputs a and b are 4-bitnumbers in 2s complement form. the output is also a 4-bit number in 2s complement form. you are allowed to use only one ttl 7483 4-bit adder to implement all the functions. but anynumber of other components (except the adder) can be used. hint: design a combinational logic circuit to modify the input b and the “carry input” of theadder depending on the control inputs s0 and s1.important: lab grade will depend on the working of the circuit & will be checked of by your labinstructor.1. is the output valid for the following input combinations: a. s0 = 0, s1 = 0, a = 7, b = 3? b. s0 = 0, s1 = 1, a = 7, b = 3? c. s0 = 1, s1 = 0, a = -4, b = -5? d. s0 = 1, s1 = 1, a = -8, b = 6? 2. what is the range of inputs (for both a and b) that will produce the valid output for all the functions?

Freya realizes she does not have enough in her bank account to use the debit card. she decides to use a credit card instead. which questions should freya answer before using a credit card? check all that apply. can i pay at least the minimum payment each month? can i make payments on time and avoid late fees? will i have to take out a loan? how much in finance charges can i afford to pay? should i talk to a consumer credit counseling service?

Why would a business likely use a java applet - to back up their data files for the business - to create a program that a customer can launch in their web browser - to create music on a powerpoint presentation - to organize files on their company directory