Design a modulo-6 counter, which counts in the sequence 0, 1, 2, 3, 4, 5, 0, the counter counts the clock pulses if its enable input w is equal to 1, otherwise it does not increment its count. use d (lip-flops in your circuit and include the state diagram, state-assigned table, next-state expressions and output expressions all clearly labeled.

Suppose we have a byte addressable computer that has a 32-byte cache with 8 bytes per block. the memory address is 8 bits long. the system accesses memory addresses (in hex) in this exact order: 6e, b9, 17, e0, 4e, 4f, 50, 91, a8, ab, ad, 93, and 94. (a) assuming the cache is direct mapped, what memory addresses will be in cache block 2 after the last address has been accessed? (b) assuming the cache is direct mapped, what is the hit ratio for the entire memory reference sequence given, assuming the cache is initially empty? (c) assuming the cache is 2-way set associative with a lru replacement policy, what is the hit ratio?

Under which key category do the page up and page down keys fall? page up and page down keys fall under the keys category.

2pointswho was mikhail gorbachev? oa. a russian leader who opposed a coupob. a polish leader who founded the labor union "solidarityoc. a soviet leader who called for a closer relationship with the unitedstates, economic reform, and a more open societyd. a soviet leader who called for more oppression in the soviet union