This problem has been solved! see the answercaches are important to providing a high performance hierarchy to processors. below is a list of 32-bit memory address references, given as word addresses.3, 180, 43, 2, 191, 88, 14, 111, 181, 44, 111, 2531) for each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 16 one-word blocks. list if each reference is a hit or miss, assuming the cache is initially empty.2) for each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with two-word blocks and a total size of 8 blocks. also list if each reference is a hit or a miss, assuming the cache is initially empty.3) you are asked to optimize a cache design for the given references. there are three direct-mapped cache designs possible, all with a total of 8 words of data: c1 has 1-word blocks, c2 has 2-word blocks, and c3 has 4-word blocks. in terms of miss rate, which cache design is the best? if the miss stall time is 25 cycles, and c1 has an access time of 2 cycles, c2 takes 3 cycles, and c3 takes 5 cycles, which is the best cache design? there are many different design parameters that are imprtant to a cache's overall performance. below are listed parameters for different direct-mapped cache designs. cache data size: 32 kibcache block size: 2 wordscache acces time: 1 cycle4) calculate the total number of bits required for the cache listed above, assuming a 32-bit address. given the total size, find the total size of the closest direct-mapped cache with 16-word blocks of equal size or greater. explain why the second cache, despite its larger data size, might provide slower performance than the first cache.5) generate a series of read requests that have a lower miss rate on a 2 kib 2-way set associative cache than the cache listed above. identify one possible solution that would make the cache listed have an equal or lower mis rate than the 2 kib cache. discuss the advantages and disadvantages of such a solution.